K 10
svn:author
V 4
loos
K 8
svn:date
V 27
2017-05-17T22:05:07.362046Z
K 7
svn:log
V 245
Fix the offset for the CPU0 MPIC registers.

Please note that only a subset of CPU0 registers are exported.  CPU1
registers are not touched.

Obtained from:	ARMADA38X Functional Specifications
Sponsored by:	Rubicon Communications, LLC (Netgate)

END