K 10
svn:author
V 6
marius
K 8
svn:date
V 27
2017-05-18T20:46:27.611754Z
K 7
svn:log
V 1360
MFC: r315598

o Add support for eMMC DDR bus speed mode up to 52 MHz to sdhci(4)
  and mmc(4). Given that support for DDR52 is not denoted by SDHCI
  capability registers, availability of that timing is indicated by
  a new quirk SDHCI_QUIRK_MMC_DDR52 and only enabled for Intel SDHCI
  controllers so far.

  Compared to 50 MHz at SDR high speed typically yielding ~45 MB/s
  read throughput with the eMMC chips tested, read performance goes
  up to ~80 MB/s at DDR52.

  As a side-effect, this change also fixes communication with some
  eMMC devices at SDR high speed mode due to the signaling voltage
  and UHS bits in the SDHCI controller no longer being left in an
  inappropriate state.

o In sdhci(4), add two tunables hw.sdhci.quirk_clear as well as
  hw.sdhci.quirk_set, which (when hooked up in the front-end)
  allow to set/clear sdhci(4) quirks for debugging and testing
  purposes. However, especially for SDHCI controllers on the
  PCI bus which have no specific support code so far and, thus,
  are picked up as generic SDHCI controllers, hw.sdhci.quirk_set
  allows for setting the necessary quirks (if required).

o In mmc(4), check and handle the return values of some more
  function calls instead of assuming that everything went right.
  In case failures actually are not problematic, indicate that
  by casting the return value to void.

END