K 10
svn:author
V 8
jhibbits
K 8
svn:date
V 27
2017-06-27T01:57:22.702707Z
K 7
svn:log
V 272
Disable interrupts when updating the TLB

Without disabling interrupts it's possible for another thread to preempt
and update the registers post-read (tlb1_read_entry) or pre-write
(tlb1_write_entry), and confuse the kernel with mixed register states.

MFC after:	2 weeks

END