K 10
svn:author
V 3
avg
K 8
svn:date
V 27
2017-12-04T17:02:53.930632Z
K 7
svn:log
V 360
amd-vi: clear event interrupt and overflow bits upon handling the interrupt

This ensures that we can receive further event interrupts.
See the description of the bits in the specification for
MMIO Offset 2020h IOMMU Status Register.
The bits are defined as set-by-hardware write-1-to-clear, same as all
the bits in the status register.

Discussed with:	anish

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