K 10
svn:author
V 2
br
K 8
svn:date
V 27
2018-01-18T18:19:31.310140Z
K 7
svn:log
V 174
UART Clock Selection Register holds a divider value for a supplied clock,
not a final baud rate. The value for this register has to be calculated.

Sponsored by:	DARPA, AFRL

END