K 10
svn:author
V 4
manu
K 8
svn:date
V 27
2018-05-17T14:51:22.249244Z
K 7
svn:log
V 368
aw_spi: Fix some silly clock mistake

The module uses the mod clock and not the ahb one.
We need to set the mod clock to twice the speed requested as the smallest
divider in the controller is 2.
The clock test function weren't calculating the register value best on the
best div but on the max one.
The cdr2 test function was using the cdr1 formula.

Pointy Hat: manu

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