K 10
svn:author
V 6
marius
K 8
svn:date
V 27
2018-09-13T09:26:16.255381Z
K 7
svn:log
V 390
MFC: r333613

The broken DDR52 support of Intel Bay Trail eMMC controllers rumored
in the commit log of r321385 has been confirmed via the public VLI54
erratum. Thus, stop advertising DDR52 for these controllers.
Note that this change should hardly make a difference in practice as
eMMC chips from the same era as these SoCs most likely support HS200
at least, probably even up to HS400ES.

END