K 10 svn:author V 4 manu K 8 svn:date V 27 2019-02-27T14:20:28.622275Z K 7 svn:log V 370 arm64: rockchip: clk_pll: Multiple improvement Remove the mode_val from the clock definition as it's a bit unreadable. Use mode_shift to represent which bit control the mode in the register. Simplify some case where we can avoid a register read before changing it. Set the PLL back to normal mode after the PLL have stabilized. Discussed with: mmel MFC after: 1 week END