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2019-06-04T15:32:56.355463Z
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MFC r347225:

Provide a template for busdma code for RISC-V.

RISC-V ISA specifies no cache management instructions so leave cache
operations in cpufunc.h as no-op for now.

Note some new hardware comes with their own memory-mapped cache
management controller.

Tested on HiFive Unleashed board with cgem(4).

Sponsored by:	DARPA, AFRL

END