K 10
svn:author
V 3
ian
K 8
svn:date
V 27
2019-08-11T22:31:38.323837Z
K 7
svn:log
V 2123
MFC r350104, r350106, r350185, r350203

r350104:
Handle the PCF2127 RTC chip the same as PCF2129 when init'ing the chip.

This affects the detection of 24-hour vs AM/PM mode... the ampm bit is in a
different location on 2127 and 2129 chips compared to other nxp rtc chips.
I noticed the 2127 case wasn't being handled correctly when I accidentally
misconfiged my system by claiming my PCF2129 was a 2127.

r350106:
Fix a paste-o, set is212x = false for other chip types.  Doh!

r350185:
Rewrite the nxprtc chip init to extend battery life by using power-saving
features offered by the chips.

For 2127 and 2129 chips, fix the detection of when chip-init is needed.  The
chip config needs to be reset whenever power was lost, but the logic was
wrong for 212x chips (it only worked for 8523).  Now the "oscillator
stopped" bit rather than the power manager mode is used to detect startup
after powerfail.

For all chips, disable the clock output pin.

For chips that have a timestamp/tamper-monitor feature, turn off monitoring
of the timestamp trigger pin.

The 8523, 2127, and 2129 chips have a "power manager" feature that offers
several options.  We've been using the default mode which enables
everything.  Now the code sets the power manager options to

 - direct-switch (when Vdd < Vbat, without extra threshold check)
 - no battery monitor
 - no external powerfail monitor

This reduces the current draw while running on battery from 1930nA to 880nA,
which should roughly double the lifespan of the battery under load.

Because battery checking is a nice thing to have, the code now does a check
at startup, and then once a day after that, instead of checking continuously
(but only actually reporting at startup).  The battery check is now done by
setting the power manager back to default mode, sleeping briefly while it
makes a voltage measurement, then switching back to power-saving mode.

r350203:
Add support for setting the aging/frequency-offset register via sysctl.

The 2127 and 2129 chips support a frequency tuning value in the range of
-7 through +8 PPM; add a sysctl handler to read and set the value.

END