K 10
svn:author
V 3
alc
K 8
svn:date
V 27
2019-09-18T14:27:09.556208Z
K 7
svn:log
V 437
MFC r350546
  Because of AArch64's weak memory consistency model, we need to include a
  memory barrier between the stores for initializing a page table page and
  the store for adding that page to the page table.  Otherwise, a page table
  walk by another processor's MMU could see the page table page before it
  sees the initialized entries.

  Simplify pmap_growkernel().  In particular, eliminate an unnecessary TLB
  invalidation.

END