K 10
svn:author
V 8
gallatin
K 8
svn:date
V 27
2019-11-07T19:54:24.508546Z
K 7
svn:log
V 757
hwpmc : fix AMD perf counter MSR access

- amd_intr() does not account for the offset (0x200) in the counter
MSR address and ends up accessing invalid regions while reading
counter value after the 4th counter (0xC001000[8,9,..]) and
erroneously updates the counter values for counters [1-4].

- amd_intr() should only check core pmcs for interrupts since
 other types of pmcs (L3,DF) cannot generate interrupts.

- fix pmc NMI's being ignored due to NMI latency on newer AMD processors

Note that this fixes a kernel panic due to GPFs accessing MSRs on
higher core count AMD cpus (seen on both Rome 7502P, and
Threadripper 2990WX 32-core CPUs)

Discussed with: markj

Submitted by:	Shreyank Amartya
Differential Revision:	https://reviews.freebsd.org/D21553

END