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dim
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2019-11-21T20:22:07.894673Z
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Merge commit 7bed381ea from llvm git (by Simon Atanasyan):

  [mips] Implement Octeon+ `saa` and `saad` instructions

  `saa` and `saad` are 32-bit and 64-bit store atomic add instructions.

     memory[base] = memory[base] + rt

  These instructions are available for "Octeon+" CPU. The patch adds
  support for both instructions to MIPS assembler and diassembler and
  introduces new CPU type - "octeon+".

  Next patches will implement `.set arch=octeon+` directive and
  `AFL_EXT_OCTEONP` ISA extension flag support.

  Differential Revision: https://reviews.llvm.org/D69849

This is one of the upstream changes needed for adding support for the
OCTEON+ CPU type, so that we can test Clang builds using the most
commonly available FreeBSD/mips64 reference platform, the Edge Router
Lite.

Requested by:	kevans
MFC after:	1 month
X-MFC-With:	r353358

END