K 10
svn:author
V 3
jhb
K 8
svn:date
V 27
2020-05-08T15:05:05.133223Z
K 7
svn:log
V 1908
MFC 354603,354604,354717,354718: Sync PLIC code with head.

354603:
plic: fix PLIC_MAX_IRQS

The maximum number of PLIC interrupts is defined in the PLIC spec[1]
as 1024.

354604:
plic: check for sifive compatible string

The Linux dts for the HiFive Unleashed does not contain the usual
"riscv,plic0" compat string, but our PLIC driver is compatible.

354717:
plic: fix context calculation

The RISC-V PLIC (platform level interrupt controller) registers are divided up
by "context", which is purposefully left ambiguous in the PLIC spec. Currently
we assume each CPU number corresponds 1-to-1 with a context number, but that is
not correct. Most existing PLIC implementations (such as SiFive's) have
multiple contexts per-cpu. For example, a single CPU might have a context for
machine mode interrupts and a context for supervisor mode interrupts. To
complicate things further, FreeBSD renumbers the CPUs during boot, but the PLIC
driver still assumes that CPU ID equals the RISC-V hart number, meaning
interrupt enables/claims might be performed for the wrong context registers.

To fix this, we must calculate each CPU's context number during
attachment. This is done by reading the interrupt properties from the
device tree, from which a mapping from context to RISC-V hart to CPU
number can be created.

354718:
plic: support irq distribution

Our PLIC implementation only enables interrupts on the boot cpu.
Implement plic_bind_intr() so that they can be redistributed near the
end of boot during intr_irq_shuffle().

This also slightly modifies how enable bits are handled in an attempt to
better fit the PIC interface. plic_enable_intr()/plic_disable_intr() are
converted to manage an interrupt source's threshold value, since this
value can be used as to globally enable/disable an irq. All handing of the
per-context enable bits is moved to the new methods plic_setup_intr()
and plic_bind_intr().

END