K 10 svn:author V 2 mw K 8 svn:date V 27 2020-05-25T14:31:32.581506Z K 7 svn:log V 678 Add QorIQ platform clockgen driver. This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs. As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts. This is a preparation patch for NXP LS1046A SoC support. Submitted by: Dawid Gorecki Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351 END