K 10
svn:author
V 4
mmel
K 8
svn:date
V 27
2020-12-14T13:10:19.267316Z
K 7
svn:log
V 414
Finish implementation of ARM PMU interrupts.
The ARM PMU may use single per-core interrupt or may use multiple generic
interrupts, one per core. In this case, special attention must be paid to
the correct identification of the physical location of the core, its order
in the external database (FDT) and the associated cpuid.

Also keep in mind that a SoC can have multiple different PMUs
(usually one per cluster)

END