K 10
svn:author
V 3
mav
K 8
svn:date
V 27
2021-08-11T00:51:48.501208Z
K 7
svn:log
V 563
Do not expose to scheduler caches of single CPU.

Before this change my dual-Xeon(R) Gold 6242R always reported 3 levels
or topology (root, package/L3 and core/L2).  But with SMT disabled
core/L2 matches thread, so additional topology level only causes more
traversal work.  With this change SMT case is reported same as before,
while non-SMT is reported with only 2 much more simple levels.

MFC after:	2 weeks

(cherry picked from commit 5a49f1914178c5275105f2ab0d23a98118cd585f)

Git Hash:   70a137b75e149611c101cb57e0322e370f669094
Git Author: mav@FreeBSD.org
END