K 10
svn:author
V 8
groudier
K 8
svn:date
V 27
2001-01-28T19:58:21.000000Z
K 7
svn:log
V 515
A couple of chip errata work-arounds refined:
- When used on a 33MHz PCI BUS, the 53C1010-66 revision 0
  requires extra clocks to be inserted in data out phase.
  Revision 1 is fixed.
- The 53C1010-33 revision 1 requires internal cycles to be
  disabled due to possible contentions on IO registers.
  Revision 2 is fixed.
Fix:
- The probing of HVD from GPIO3 bit by the driver was reversed.
  The driver could misprobe the bus mode of a 825 or 875 chip
  that was not previously initialized (no BIOS for example).

END