K 10
svn:author
V 3
tmm
K 8
svn:date
V 27
2002-07-12T16:26:49.000000Z
K 7
svn:log
V 385
When sending cache flushing IPIs, don't try to IPI the triggering CPU
itself; this causes undefined behaviour on UltraSPARCs. In particular,
the interrupt packet data words will not necessarily be delivered
correctly, which would result in a crash.
This bug also caused the cache-flushing work to be done twice on the
triggering CPU (when it did not cause crashes).

Reviewed by:	jake

END