DELTA 277156 0 37
SVN ƒŸ2ƒ¢Uƒ  ÏL € † ÏJ€‚ ÉkÕGƒ/* Global cache line sizes, use 32 as default */
int	arm_dcache_min_line_size = 32;
int	arm_icache_min_line_size = 32;
int	arm_idcache_min_line_size = 32;/* Resolve minimal cache line sizes */
		arm_dcache_min_line_size = 1 << (CPU_CT_DMINLINE(ctype) + 2);
		arm_icache_min_line_size = 1 << (CPU_CT_IMINLINE(ctype) + 2);
		arm_idcache_min_line_size =
		    min(arm_icache_min_line_size, arm_dcache_min_line_size);
ENDREP
DELTA 272209 0 470
SVN Ä9Å~,ƒO+ Ž' €I ’.Ž"€L ‚¢³ ƒ¤6³ ‚"§i´ „bª!ž •-¯ƒMarmv7_dcache_line_size:
	.word	_C_LABEL(arm_dcache_min_line_size)
.Larmv7_icache_line_size:
	.word	_C_LABEL(arm_icache_min_line_size)
.Larmv7_idcache_line_size:
	.word	_C_LABEL(arm_idcache_min_line_sizENTRY(armv7_dcache_wb_range)
	ldr	ip, .Larmv7_dcache_line_size
	ldr	ip, [ip]     ip, .Larmv7_dcache_line_size
	ldr     ip, [ip]     ip, .Larmv7_dcache_line_size
	ldr     ip, [ip]     ip, .Larmv7_idcache_line_size
	ldr     ip, [ip]icache_line_size
	ldr	ip, [ip]ENDREP
DELTA 262958 223 30
SVN ž¡Vƒ4  ( €t Ÿ %€‚> Þg¿7ƒ2int     arm_dcache_min_line_size = 32;
int     arm_icache_min_line_size = 32;
int     arm_idcache_min_line_size = 32/* Resolve minimal cache line sizes */
		arm_dcache_min_line_size = 1 << (CPU_CT_DMINLINE(ctype) + 2);
		arm_icache_min_line_size = 1 << (CPU_CT_IMINLINE(ctype) + 2);
		arm_idcache_min_line_size =
		    (arm_dcache_min_line_size > arm_icache_min_line_size ?
		    arm_icache_min_line_size : arm_dcache_min_line_size);
ENDREP
DELTA 277156 154 43
SVN ’v”,7 ëc €5 §ëb5/* Cache type register definitions for ARM v7 */
#define	CPU_CT_IMINLINE(x)	((x) & 0xf)		/* I$ min line size */
#define	CPU_CT_DMINLINE(x)	(((x) >> 16) & 0xf)	/* D$ min line size */ENDREP
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autoconf.c
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file 5-129198.0.r146794/7877
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bcopy_page.S
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bcopyinout.S
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bcopyinout_xscale.S
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blockio.S
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cpufunc_asm_armv4.S
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cpufunc_asm_armv5.S
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cpufunc_asm_armv6.S
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cpufunc_asm_armv7.S
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cpufunc_asm_xscale_c3.S
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db_interface.c
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db_trace.c
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devmap.c
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disassem.c
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file 1m-129198.0.r269956/12421
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dump_machdep.c
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file 1o-129198.0.r276772/20464
K 13
elf_machdep.c
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elf_note.S
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elf_trampoline.c
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exception.S
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fiq.c
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fiq_subr.S
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file 1w-129198.0.r262980/2073
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fusu.S
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file 1y-129198.0.r276596/3227
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gdb_machdep.c
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file 4-160332.0.r276190/7485
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genassym.c
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generic_timer.c
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file 4-252372.0.r275208/78
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gic.c
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identcpu.c
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in_cksum.c
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in_cksum_arm.S
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file 26-129198.0.r275418/2607
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inckern.S
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file 7-150861.0.r159557/2076
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intr.c
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file 28-129198.0.r277835/16119
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locore-v4.S
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file 2c-129198.0-276396.r277416/59
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locore-v6.S
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file 5-276396.0.r277305/505
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locore.S
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machdep.c
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mem.c
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file 4-137362.0.r277743/180
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minidump_machdep.c
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file d-184728.0.r272766/8738
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mp_machdep.c
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mpcore_timer.c
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mpcore_timervar.h
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pmap.c
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file 2m-129198.0.r271422/902
K 5
pmu.c
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file 4-277745.0.r277745/1951
K 12
sc_machdep.c
V 28
file 4-239696.0.r239696/1083
K 9
setcpsr.S
V 29
file 2o-129198.0.r261393/4262
K 10
setstack.s
V 29
file 2q-129198.0.r269390/5808
K 15
stack_machdep.c
V 28
file k-174195.0.r276190/8387
K 11
stdatomic.c
V 27
file 4-251695.0.r275564/197
K 9
support.S
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K 7
swtch.S
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K 13
sys_machdep.c
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K 9
syscall.c
V 34
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K 9
trap-v6.c
V 27
file 4-276638.0.r277523/183
K 6
trap.c
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file 2y-129198.0.r276206/858
K 13
uio_machdep.c
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file 30-129198.0.r263059/3428
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undefined.c
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vfp.c
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END
ENDREP
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acle-compat.h
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armreg.h
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asm.h
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asmacros.h
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frame.h
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machdep.h
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md_var.h
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memdev.h
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ptrace.h
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END
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xilinx
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xscale
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END
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amd64
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arm
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boot
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bsm
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cam
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cddl
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