DELTA 328177 0 350 SVN&(m&Yrf~?phH |} R.E^ * K3I1)4;o1kI1* SZ\o$d|^yx^T]o0}}(E=y#FhTB8f0&Mg\F4դi{=]+8hw_ibrs_recalculate();ENDREP DELTA 328199 0 114 SVNJ6 5UNABLE_INT_FETCH("hw.ibrs_disable", &hw_ibrs_disable)ENDREP DELTA 328470 7026 405 SVN=N -&@Jx^TMo0 =˿B:oP`ć`EboHrҎtEH3 ,|[|Ʌ쾤XZKPT+ &iJvGN]Q7 ihy*q '>aMQ%V[?0 C@j.[ei2e|) A4i' ws$<.Q:M t²$G"G g,gלewI S3%4==p[X(dj 9ӧ,^?Jes_Ĺc֎y7joTHG H̺?ijZv<R{S~QC|E3 TEENDREP DELTA 328083 11107 170 SVN!9 # T!D]!movq %rax,TF_RAX(%rsp) movq %rdx,TF_RDX(%rsp) movq %rcx,TF_RCX(%rsp) call handle_ibrs_entry sti movq %rsi,TF_RSI(%rsp) movq %r8,TF_R8(%rsp) movq %r9,TF_R9ENDREP DELTA 271076 177 802 SVN[Rlk\%tx"99x^mk@_18W6%ȡ ,QtHw֊L?r~{rm<›VC8}ۧͻ]Ax Uh}7b֟K>*{bl\hh,.vN2TjLL eGA-w5C"wm$>^gWe5LNMEX4Ͼ>j ]FC(¡>6ikwsSoaZBpب#{C.bBQgU,PؔeWii).P}cN{Nu4pq8uZP gIX::^ƀ.9TcKNֿ@}A%ֽOENDREP DELTA 328177 2059 48 SVNPn - .<,uint32_t pc_ibpb_set; \ char __pad[216ENDREP DELTA 327963 0 36 SVN  Q7Lhw_ibrs_recalculateENDREP DELTA 327834 148 121 SVN4k4jj ENTRY(handle_ibrs_entry) ret END(handle_ibrs_entry) ENTRY(handle_ibrs_exit) ret END(handle_ibrs_exit) ENDREP DELTA 327964 0 306 SVN+>aM^ * IA32_SPEC_CTRL and IA32_PRED_CMD MSRs are described in the Intel' * document 336996-001 Speculative Execution Side Channel Mitigations. */ENDREP DELTA 328166 81 37 SVNjE S hR _Rhandle_ibrs_entry(void); void handle_ibrs_exit(void); void hw_ibrs_recalculate(voiENDREP DELTA 325892 789 22 SVNK{ uc{4[0x^T]o0}&i/@[$heX If;t}iҴH@{Ϲ_BR׬P yQo* )_KPUp .`Eb2@V,sxY@%JrI9Ks@4FSP )k:珸V@lA/=Ma@SMWbP%~ *&< s=ghh —Bx-WűOYPLo.RFҲȋ}261q܁woH8v`pc>UA{"9 0^}FlнW`IUN/*$0n C\·Dی@k)($( &$ Fbbk#:1'`dj7T-