DELTA 357591 0 264 SVN  DMHSCAUSEENDREP DELTA 357595 0 41 SVNl } ^{m{SCAUSE_INTR (1ul << 63) #define SCAUSE_CODE (~SCAUSE_INTR) #define SCAUSE_INST_MISALIGNED 0 #define SCAUSE_INST_ACCESS_FAULT 1 #define SCAUSE_ILLEGAL_INSTRUCTION 2 #define SCAUSE_BREAKPOINT 3 #define SCAUSE_LOAD_MISALIGNED 4 #define SCAUSE_LOAD_ACCESS_FAULT 5 #define SCAUSE_STORE_MISALIGNED 6 #define SCAUSE_STORE_ACCESS_FAULT 7 #define SCAUSE_ECALL_USER 8 #define SCAUSE_ECALL_SUPERVISOR 9 #define SCAUSE_INST_PAGE_FAULT 12 #define SCAUSE_LOAD_PAGE_FAULT 13 #define SCAUSE_STORE_PAGE_FAULT 15ENDREP DELTA 364180 85 286 SVNer N &LeL(tf->tf_scause & SCAUSE_INTR) != 0) db_printf("--- interrupt %ld\n", tf->tf_scause & SCAUSE_CODE); else db_printf("--- exception %ld, tval = %#lx\n", tf->tf_scause & SCAUSE_CODEENDREP DELTA 366515 0 147 SVNal &G(frame->tf_scause & SCAUSE_INTR) != 0, ("riscv_cpu_intr: wrong frame passed")); active_irq = frame->tf_scause & SCAUSE_CODEENDREP DELTA 366534 0 98 SVN]CKcJZSdX@[