K 10 svn:author V 5 tobik K 8 svn:date V 27 2018-06-06T13:47:33.331240Z K 7 svn:log V 359 New port: devel/arachne-pnr Arachne-pnr implements the place and route step of the hardware compilation process for FPGAs. It currently targets the Lattice Semiconductor iCE40 family of FPGAs. WWW: https://github.com/cseed/arachne-pnr PR: 227590 Submitted by: Johnny Sorocil Differential Revision: https://reviews.freebsd.org/D15632 END