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tobik
K 8
svn:date
V 27
2018-06-06T14:19:51.489984Z
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V 359
New port: devel/yosys

Yosys is a framework for Verilog RTL synthesis.  It currently has
extensive Verilog-2005 support and provides a basic set of synthesis
algorithms for various application domains.

WWW: http://www.clifford.at/yosys/

PR:		227591
Submitted by:	Johnny Sorocil <jsorocil@gmail.com>
Differential Revision:	https://reviews.freebsd.org/D15632

END