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SVN ££T'
 ˜O ¦ Š_˜?&iscv-fesvr
    SUBDIR += riscv-isa-simENDREP
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SVN  UW€UUTIMESTAMP = 1486479769
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ENDREP
DELTA
SVN  ‚ ‚€‚ ‚ RISC-V Frontend Server

The RISC-V front-end server library, which facilitates communication between a
host machine and a RISC-V target machine. It is usually not meant to be used as
a standalone package.

WWW: https://github.com/freebsd-riscv/riscv-fesvr
ENDREP
DELTA
SVN  ƒ%ƒ'€ƒ%ƒ%bin/elf2hex
include/fesvr/configstring.h
include/fesvr/context.h
include/fesvr/device.h
include/fesvr/dtm.h
include/fesvr/elf.h
include/fesvr/elfloader.h
include/fesvr/htif_hexwriter.h
include/fesvr/htif_pthread.h
include/fesvr/htif.h
include/fesvr/memif.h
include/fesvr/option_parser.h
include/fesvr/rfb.h
include/fesvr/syscall.h
include/fesvr/term.h
include/fesvr/tsi.h
lib/libfesvr.so
libdata/pkgconfig/riscv-fesvr.pc
ENDREP
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DELTA
SVN  Y[€YYTIMESTAMP = 1486479711
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ENDREP
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DELTA
SVN  ‚‚€‚‚--- riscv/insn_template.cc.orig	2016-08-01 15:40:47 UTC
+++ riscv/insn_template.cc
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-#include "insn_template.h"
+#include "insn_template.hpp"
 
 reg_t rv32_NAME(processor_t* p, insn_t insn, reg_t pc)
 {
ENDREP
DELTA
SVN  ‚X‚Z€‚X‚X--- riscv/riscv.mk.in.orig	2016-08-01 15:40:47 UTC
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@@ -21,13 +21,13 @@ riscv_hdrs = \
 	tracer.h \
 	extension.h \
 	rocc.h \
-	insn_template.h \
+	insn_template.hpp \
 	mulhi.h \
 	gdbserver.h \
 	debug_module.h \
 
 riscv_precompiled_hdrs = \
-	insn_template.h \
+	insn_template.hpp \
 
 riscv_srcs = \
 	processor.cc \
ENDREP
DELTA
SVN  -/€--Spike, a RISC-V ISA Simulator

The RISC-V ISA Simulator implements a functional model of one or more RISC-V
processors.

WWW: https://github.com/freebsd-riscv/riscv-isa-sim
ENDREP
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